SSE_ALL-General Support-Other

SSE_ALL-General Support-Other#

_MM_GET_EXCEPTION_STATE#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

unsigned int

Intel Description

Macro: Get the exception state bits from the MXCSR control and status register. The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT

Intel Implementation Psudeo-Code

dst[31:0] := MXCSR & _MM_EXCEPT_MASK

_MM_SET_EXCEPTION_STATE#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

void

Param Types:

unsigned int a

Param ETypes:

UI32 a

void _MM_SET_EXCEPTION_STATE(unsigned int a);

Intel Description

Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer “a”. The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT

Intel Implementation Psudeo-Code

MXCSR := a[31:0] AND ~_MM_EXCEPT_MASK

_MM_GET_EXCEPTION_MASK#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

unsigned int

Intel Description

Macro: Get the exception mask bits from the MXCSR control and status register. The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT

Intel Implementation Psudeo-Code

dst[31:0] := MXCSR & _MM_MASK_MASK

_MM_SET_EXCEPTION_MASK#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

void

Param Types:

unsigned int a

Param ETypes:

UI32 a

void _MM_SET_EXCEPTION_MASK(unsigned int a);

Intel Description

Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer “a”. The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT

Intel Implementation Psudeo-Code

MXCSR := a[31:0] AND ~_MM_MASK_MASK

_MM_GET_ROUNDING_MODE#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

unsigned int

Intel Description

Macro: Get the rounding mode bits from the MXCSR control and status register. The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO

Intel Implementation Psudeo-Code

dst[31:0] := MXCSR & _MM_ROUND_MASK

_MM_SET_ROUNDING_MODE#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

void

Param Types:

unsigned int a

Param ETypes:

UI32 a

void _MM_SET_ROUNDING_MODE(unsigned int a);

Intel Description

Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer “a”. The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO

Intel Implementation Psudeo-Code

MXCSR := a[31:0] AND ~_MM_ROUND_MASK

_MM_GET_FLUSH_ZERO_MODE#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

unsigned int

Intel Description

Macro: Get the flush zero bits from the MXCSR control and status register. The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF

Intel Implementation Psudeo-Code

dst[31:0] := MXCSR & _MM_FLUSH_MASK

_MM_SET_FLUSH_ZERO_MODE#

Tech:

SSE_ALL

Category:

General Support

Header:

immintrin.h

Searchable:

SSE_ALL-General Support-Other

Return Type:

void

Param Types:

unsigned int a

Param ETypes:

UI32 a

void _MM_SET_FLUSH_ZERO_MODE(unsigned int a);

Intel Description

Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer “a”. The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF

Intel Implementation Psudeo-Code

MXCSR := a[31:0] AND ~_MM_FLUSH_MASK
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