AVX_ALL-Store-YMM

AVX_ALL-Store-YMM#

_mm256_store_pd#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

double * mem_addr, __m256d a

Param ETypes:

FP64 mem_addr, FP64 a

void _mm256_store_pd(double * mem_addr, __m256d a);

Intel Description

Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from “a” into memory.

“mem_addr” must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_store_ps#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

float * mem_addr, __m256 a

Param ETypes:

FP32 mem_addr, FP32 a

void _mm256_store_ps(float * mem_addr, __m256 a);

Intel Description

Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from “a” into memory.

“mem_addr” must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_storeu_pd#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

double * mem_addr, __m256d a

Param ETypes:

FP64 mem_addr, FP64 a

void _mm256_storeu_pd(double * mem_addr, __m256d a);

Intel Description

Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from “a” into memory.

“mem_addr” does not need to be aligned on any particular boundary.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_storeu_ps#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

float * mem_addr, __m256 a

Param ETypes:

FP32 mem_addr, FP32 a

void _mm256_storeu_ps(float * mem_addr, __m256 a);

Intel Description

Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from “a” into memory.

“mem_addr” does not need to be aligned on any particular boundary.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_store_si256#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

__m256i * mem_addr, __m256i a

Param ETypes:

M256 mem_addr, M256 a

void _mm256_store_si256(__m256i * mem_addr, __m256i a);

Intel Description

Store 256-bits of integer data from “a” into memory.

“mem_addr” must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_storeu_si256#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

__m256i * mem_addr, __m256i a

Param ETypes:

M256 mem_addr, M256 a

void _mm256_storeu_si256(__m256i * mem_addr, __m256i a);

Intel Description

Store 256-bits of integer data from “a” into memory.

“mem_addr” does not need to be aligned on any particular boundary.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_maskstore_pd#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

double * mem_addr, __m256i mask, __m256d a

Param ETypes:

FP64 mem_addr, MASK mask, FP64 a

void _mm256_maskstore_pd(double* mem_addr, __m256i mask,
                         __m256d a)

Intel Description

Store packed double-precision (64-bit) floating-point elements from “a” into memory using “mask”.

Intel Implementation Psudeo-Code

FOR j := 0 to 3
        i := j*64
        IF mask[i+63]
                MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
        FI
ENDFOR

_mm256_maskstore_ps#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

float * mem_addr, __m256i mask, __m256 a

Param ETypes:

FP32 mem_addr, MASK mask, FP32 a

void _mm256_maskstore_ps(float* mem_addr, __m256i mask,
                         __m256 a)

Intel Description

Store packed single-precision (32-bit) floating-point elements from “a” into memory using “mask”.

Intel Implementation Psudeo-Code

FOR j := 0 to 7
        i := j*32
        IF mask[i+31]
                MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
        FI
ENDFOR

_mm256_stream_si256#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

void* mem_addr, __m256i a

Param ETypes:

M256 mem_addr, M256 a

void _mm256_stream_si256(void* mem_addr, __m256i a);

Intel Description

Store 256-bits of integer data from “a” into memory using a non-temporal memory hint.

“mem_addr” must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_stream_pd#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

void* mem_addr, __m256d a

Param ETypes:

FP64 mem_addr, FP64 a

void _mm256_stream_pd(void* mem_addr, __m256d a);

Intel Description

Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from “a” into memory using a non-temporal memory hint.

“mem_addr” must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_stream_ps#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

void* mem_addr, __m256 a

Param ETypes:

FP32 mem_addr, FP32 a

void _mm256_stream_ps(void* mem_addr, __m256 a);

Intel Description

Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from “a” into memory using a non-temporal memory hint.

“mem_addr” must be aligned on a 32-byte boundary or a general-protection exception may be generated.

Intel Implementation Psudeo-Code

MEM[mem_addr+255:mem_addr] := a[255:0]

_mm256_storeu2_m128#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

float* hiaddr, float* loaddr, __m256 a

Param ETypes:

FP32 hiaddr, FP32 loaddr, FP32 a

void _mm256_storeu2_m128(float* hiaddr, float* loaddr,
                         __m256 a)

Intel Description

Store the high and low 128-bit halves (each composed of 4 packed single-precision (32-bit) floating-point elements) from “a” into memory two different 128-bit locations.

“hiaddr” and “loaddr” do not need to be aligned on any particular boundary.

Intel Implementation Psudeo-Code

MEM[loaddr+127:loaddr] := a[127:0]
MEM[hiaddr+127:hiaddr] := a[255:128]

_mm256_storeu2_m128d#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

double* hiaddr, double* loaddr, __m256d a

Param ETypes:

FP64 hiaddr, FP64 loaddr, FP64 a

void _mm256_storeu2_m128d(double* hiaddr, double* loaddr,
                          __m256d a)

Intel Description

Store the high and low 128-bit halves (each composed of 2 packed double-precision (64-bit) floating-point elements) from “a” into memory two different 128-bit locations.

“hiaddr” and “loaddr” do not need to be aligned on any particular boundary.

Intel Implementation Psudeo-Code

MEM[loaddr+127:loaddr] := a[127:0]
MEM[hiaddr+127:hiaddr] := a[255:128]

_mm256_storeu2_m128i#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

__m128i* hiaddr, __m128i* loaddr, __m256i a

Param ETypes:

M128 hiaddr, M128 loaddr, M128 a

void _mm256_storeu2_m128i(__m128i* hiaddr, __m128i* loaddr,
                          __m256i a)

Intel Description

Store the high and low 128-bit halves (each composed of integer data) from “a” into memory two different 128-bit locations.

“hiaddr” and “loaddr” do not need to be aligned on any particular boundary.

Intel Implementation Psudeo-Code

MEM[loaddr+127:loaddr] := a[127:0]
MEM[hiaddr+127:hiaddr] := a[255:128]

_mm256_maskstore_epi32#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

int* mem_addr, __m256i mask, __m256i a

Param ETypes:

UI32 mem_addr, MASK mask, UI32 a

void _mm256_maskstore_epi32(int* mem_addr, __m256i mask,
                            __m256i a)

Intel Description

Store packed 32-bit integers from “a” into memory using “mask” (elements are not stored when the highest bit is not set in the corresponding element).

Intel Implementation Psudeo-Code

FOR j := 0 to 7
        i := j*32
        IF mask[i+31]
                MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i]
        FI
ENDFOR

_mm256_maskstore_epi64#

Tech:

AVX_ALL

Category:

Store

Header:

immintrin.h

Searchable:

AVX_ALL-Store-YMM

Register:

YMM 256 bit

Return Type:

void

Param Types:

__int64* mem_addr, __m256i mask, __m256i a

Param ETypes:

UI64 mem_addr, MASK mask, UI64 a

void _mm256_maskstore_epi64(__int64* mem_addr, __m256i mask,
                            __m256i a)

Intel Description

Store packed 64-bit integers from “a” into memory using “mask” (elements are not stored when the highest bit is not set in the corresponding element).

Intel Implementation Psudeo-Code

FOR j := 0 to 3
        i := j*64
        IF mask[i+63]
                MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i]
        FI
ENDFOR
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